Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and, thus, higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary because even relatively small defects may cause unwanted aberrations in the semiconductor devices.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitation on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. As design rules shrink, the population of potentially yield-relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. Determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process induced failures, in some cases, tend to be systematic. That is, process-induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially-systematic, electrically-relevant defects can have an impact on yield.
Defect review typically involves high resolution imaging and classification of defects that were flagged by an inspection process using either a high magnification optical system or a scanning electron microscope (SEM). Defect review is typically performed at discrete locations on specimens where defects have been detected by inspection. The higher resolution data for the defects generated by defect review is more suitable for determining attributes of the defects such as profile, roughness, or more accurate size information.
Optical inspection of a semiconductor wafer during manufacturing is generally a slow, manual process. Defect teams at semiconductor fabrication plant (fabs) usually use optical tools for wafer inspection, but typically perform SEM review of defects for verification. Thus, for every layer inspected on an optical inspection tool, a sampled population of defects is then reviewed on an SEM tool. Manual classification of the reviewed defects is tedious and time-consuming. Fabs use automatic detection and classification schemes to save the time and effort involved in defect classification. However, the automatic detection and classification schemes have limitations and are not a replacement for a human classification. Besides requiring large computation power, automatic detection and classification schemes are prone to nuisance or instances of multiple, non-important defects. An optimal inspection recipe for a semiconductor layer should detect as many defects of interest (DOIs) as possible while maintaining a substantially low nuisance rate.
Previously, pixel level quantification of defects used edge detection and computation or grey level difference based algorithms. These techniques are not flexible for process variation-induced changes in the structures of interest. Grey level changes caused by imaging artefacts are known to induce sources of error in the computation. Distinguishing between similar looking intended and process-induced random defect modes may be challenging or even impossible.
Therefore, improved techniques and systems for defect detection and classification are needed.